The present invention relates to a technology which is effective when applied to a semiconductor integrated circuit device and, more particularly, to a technology which is effective when applied to a semiconductor integrated circuit device equipped with a one-element type memory cell composed of a field effect transistor (FET) having a floating gate electrode and a control gate electrode.
A known semiconductor integrated circuit device having a nonvolatile memory function is exemplified by an EPROM (Erasable Programmable Read Only Memory) and a flash type E.sup.2 PROM (Electrically Erasable Programmable Read Only Memory).
In these semiconductor integrated circuit devices, the memory cell for data storage is constructed of a floating gate electrode, which is formed over a semiconductor substrate through a first insulating film, and a control gate electrode which is formed over the floating gate electrode through a second insulating film.
The aforementioned field effect transistor constituting the memory cell is disposed at each interconnection of data lines and word lines. Each word line is connected with control gate of the field effect transistor. This field effect transistor has its source region connected with a source line (e.g., an n-type semiconductor region), which is formed integrally therewith, and its drain region connected with a respective data line associated therewith. The drain region of the aforementioned field effect transistor and the data line are connected through a connection hole which is formed in an inter-layer insulating film covering the memory cell.
On the other hand, the element isolating region of the aforementioned field effect transistor is formed of a field insulating film which is formed by a selective oxidation.
The structure of the aforementioned memory cell is disclosed in U.S. Pat. No. 4,663,645 or 1985 IEDM Tech. Dig. pp 616 to 619, for example.